Senior Design Verification Engineer
Company: VirtualVocations
Location: Springfield
Posted on: October 30, 2024
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Job Description:
A company is looking for a Senior Design Verification Engineer
to join their team.
Key Responsibilities
Develop and execute verification plans for digital designs using
SystemVerilog and UVM
Create and maintain testbenches, test cases, and test vectors
Run simulations to verify design against specifications and analyze
results
Required Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering,
or related field
Minimum of 5 years of hands-on experience in SoC verification using
UVM
Experience using Synopsys verification tools such as VCS, Verdi,
and Spyglass
Experience writing and debugging RTL using SystemVerilog
Programming experience using C, C++, and/or Python
Keywords: VirtualVocations, New Bedford , Senior Design Verification Engineer, Engineering , Springfield, Massachusetts
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